1. Field of the Invention
The present invention relates generally to a process for fabricating a semiconductor device. More specifically, the invention relates to a process for fabricating a direct contact electrode of a MOSFET integrated circuit.
2. Description of the Related Art
concerning semiconductor devices of the type which the present invention concerns, discussion will be given in terms of a PN dual-gate CMOS semiconductor device. In a PN dual-gate CMOS semiconductor device, a P-type transistor has a P-type gate electrode, and an N-type transistor has a N-type gate electrode. The feature of such semiconductor device is the capability of suppression of short-channel effect of the P-type transistor since the channel of the P-type transistor becomes a surface-channel type. FIGS. 1A to 1L are cross sections showing the conventional fabrication process of the PN dual-gate CMOS transistor.
Initially, utilizing known technologies, an N well 302, a P well 303, a field oxide layer 304, and P-type channel stopper 305 are formed on a P-type silicon substrate 301, as shown in FIG. 1A. Then, by a thermal oxidation process, a gate oxide layer 306 in the thickness of 100 .ANG. is formed on the N well 302 and the P well 303, as shown in FIG. 1B. Thereafter, the gate oxide layer 306 at a direct contact region 307 is removed by way of photoetching, as shown in FIG. 1C.
Next, as shown in FIG. 1D, by way of chemical vapor deposition (CVD), a non-doped polycrystalline layer 308 is deposited in a thickness of the order of 3000 .ANG.. Subsequently, by photolithography and dry etching, gate electrodes 309 and a direct contact electrode 310 are formed, as shown in FIG. 1E. In this process, the ideal section is as illustrated in FIG. 1E. However, in practice, in order to avoid a residual layer after etching through the overall surface of the wafer, over-etching is inherently performed to form a pit 324 in the substrate, as shown in FIG. 2.
In order to simplify the disclosure, the following discussion will be given on the assumption that the ideal section as shown in FIG. 1E can be formed.
Next, as shown in FIG. 1F, photolithography and ion implantation are applied to form a N -type diffusion layer 311 in the region to form the N-type transistor on the surface of the substrate.
Then, as shown in FIG. 1G, photolithography and ion implantation are applied to form a P -type diffusion layer 312 in the region to form the P-type transistor on the surface of the substrate. Subsequently, by way of CVD, an insulation layer 313 is grown to a thickness of 2000 .ANG.. Thereafter, as shown in FIG. 1H, side walls 314 are formed by performing anisotrophy etching.
Then, the region to form the P-type transistor is masked by way of photolithographic technology. Thereafter, arsenic (As) is implanted in the order of 5.times.10.sup.15 cm.sup.-2 at 70 keV, and then the substrate is annealed at 900.degree. C. for 10 minutes to form N.sup.+ -type diffusion layer 315, N.sup.+ type gate electrode 316 and N.sup.+ -type diffusion layer 317 for a direct contact region of the N-type transistor, as shown in FIG. 1I.
Next, the region, in which the N-type transistor is formed, is masked by way of photolithographic technology. Thereafter, as shown in FIG. 1J, boron (B) is implanted in the order of 5.times.10.sup.15 cm.sup.-2 at 10 keV, and then the substrate is annealed at 850.degree. C. for 10 minutes to form P.sup.+ -type diffusion layer 318 and P.sup.+ type gate electrode 319 of the P-type transistor. Thereafter, by ion implantation of silicon in the order of 1.times.10.sup.15 cm.sup.-2 at 70 keV the substrate surface is transformed to an amorphous state. Subsequently, a titanium layer 320 is formed over the entire surface of the substrate to the thickness of 500 .ANG., as shown in FIG. 1J.
Next, as shown in FIG. 1K, heat treatment (rapid thermal anneal) under a nitrogen atmosphere is performed at a temperature of 700.degree. C. to selectively form a titanium silicide film 321 on the N.sup.+ -type diffusion layer 315, the N.sup.+ -type gate electrode 316, the direct contact electrode 310 of the N-type transistor, the P.sup.+ -type diffusion layer 318, and the P.sup.+ -type gate electrode 319 of the P-type transistor. Subsequently, the substrate is dipped in a mixture of aqueous ammonia and hydrogen peroxide to selectively remove titanium nitride which is nitrided and not silicided (FIG. 1K).
Then, as shown in FIG. 1L, an interlayer insulation layer 322 and wiring 323 are deposited by known technology to obtain the PN dual-gate CMOS with the direct contact of a conventional structure.
The prior art described above have been disclosed in Thomas Tang et al. "VLSI LOCAL INTERCONNECT LEVEL USING TITANIUM NITRIDE" IEDM 1985, pp 590-593, I. Sakai et al. "A NEW SALICIDE PROCESS (PASET) FOR SUB-HALF MICRON CMOS", 1992 symposium on VLSI technology Digest Technical Papers, pp. 66-67.
The conventional process for forming the direct contact as set forth above is required to perform overetching in the etching step for the non-doped polycrystalline silicon layer 308 shown in FIG. 1E so as not to leave residual over the entire surface of the wafer. However, since there is no selectivity between the non-doped polycrystalline silicon and silicon of the substrate in etching, the overetching inherently results in etching of the substrate to introduce defects in the substrate. Therefore, a junction layer leak current is increased to cause degradation of the device characteristics and lowering of yield.
Also, since the prior art requires a special photolithographic step for forming the direct contact hole, the number of process steps is increased and the process becomes complicated.